DeepSeek and Huawei Open-Source the Ascend Toolchain: TileLang for Ascend Takes Aim at CUDA

On September 30, DeepSeek announced on its official WeChat public account that it is open-sourcing a full set of infrastructure components for Huawei’s Ascend compute platform — six in total, each mapping one-to-one to a tool it had previously open-sourced for Nvidia hardware. The headliner is the Ascend edition of TileLang: a high-level language compilation tool positioned directly against Nvidia’s CUDA.

What Was Released

• TileLang: wraps the low-level Ascend C instructions of the Ascend platform so developers can write operators in a high-level language without sacrificing hardware performance.
• DeepGEMM: matrix-multiplication acceleration, supporting BF16, FP8, and FP4.
• DeepEP: multi-card distributed communication, with interfaces deliberately aligned with the Nvidia edition.
• TileKernels: vector compute and memory access, with one set of Python interfaces shared across Nvidia GPUs and Huawei NPUs.
• FlashMLA: a sparse-attention operator optimized for long-context efficiency.
• DeepSelect: TopK data filtering.

DeepSeek’s account is that this roadmap was first proven on Nvidia hardware. In the V4-series model training, the vast majority of operators were implemented in TileLang. The Ascend edition follows the same playbook: every TileLang operator used in training already has a corresponding high-performance implementation on Ascend.

Why TileLang Matters

What makes CUDA truly unassailable is more than a decade of accumulated software ecosystem and developer habits. What DeepSeek is doing is filling in that moat for Chinese chips, block by block.

According to the official introduction, TileLang is simpler than CUDA programming, improving development efficiency and simplifying code logic. Compared with other high-level languages of its kind, its programming model maps more closely to chip characteristics, getting close to the hardware’s performance ceiling.

A Supernode of 128 Ascend 950 Chips

Beyond software, the two sides jointly built a hardware proving ground: a “supernode” design built from 128 Ascend 950 chips, linked into a single logical mega-machine with deep optimization for compute and communication. Multiple tests are said to approach the hardware’s performance ceiling. Liang Wenfeng also revealed that the company currently devotes more than 70% of its compute to model training — and that once the software stack migrates to Ascend, the sources of that compute can diversify too.

Read the README’s Fine Print First

DeepSeek’s own GitHub README, though, spells out the caveats clearly. The performance numbers were produced on an unreleased, early-access concept-validation dev kit provided by Huawei, with undisclosed manual configurations. Full bandwidth has to wait for the commercial Atlas 850E dev kit, expected in mid-October.

DeepEP reaches roughly 90% to 95% of physical bandwidth for distribution at expert-parallel scales of 32 or below. Scaling further, and result aggregation performance, are still being optimized.

There are also gaps in the CUDA-equivalent layer. FlashMLA’s fused operator currently supports only the Nvidia platform; the Ascend edition isn’t there yet. The Ascend edition of DeepSelect supports only bf16, not fp32. Adopting the toolchain requires the full Ascend stack — Ascend chips, the CANN 9.2.0+ software stack, and firmware — so the bar is not low.

What to Watch Next

This release’s significance is at the software layer: for the first time, a Chinese large model could plausibly complete the full training pipeline on Ascend — from compilation to compute to communication — without falling back to Nvidia at any step. Two things to watch next: whether the commercial Atlas 850E dev kit ships on time, and whether the community can fill the remaining gaps.